1. Field of the Invention
The present invention relates to a method for driving a matrix display panel.
2. Description of the Related Art
Interest has been growing in recent years toward plasma display panels (hereafter, “PDP”) in which a plurality of discharge cells are arranged in a matrix shape as two dimensional image display panels. The number of gradations of luminance that can be expressed by a PDP depends on the number of pixel data bits for each pixel based on the video signal.
As a method for displaying gradations in a PDP, the sub-field method is known, in which the cells are driven by dividing the display period of one field into a plurality of sub-fields. In the sub-field method, the display period of one field is divided into a plurality of sub-fields. Each sub-field includes an address period in which each pixel is set to a lighted mode or an unlighted mode in accordance with the pixel data, and an emission sustain period in which only the pixels in the lighted mode are lighted (caused to emit light) for a period corresponding to the weighting of that sub-field. That is, for each sub-field, it is set whether the discharge cells are to emit light within that sub-field (address period), and the discharge cells that are set to the lighted mode emit light only for the period assigned to that sub-field (referred to as an emission sustain period). Consequently, there are occasions in which, in one field, sub-fields for a light-emitting state and sub-fields for an unlighted (non-light emitting) state, are mixed. At such time, intermediate levels of luminance corresponding to the total light emitting period of all the sub-fields can be seen.
FIG. 1 shows a schematic example of a PDP emission driving format, such as the one disclosed in Japanese Patent Kokai No. 2001-154630 for example. One field of the video signal is made up of twelve sub-fields, SF1 to SF12. Each sub-field includes an addressing step Wc, in which each discharge cell of the PDP is set to either a “lighted discharge cell mode” (that is, an operative mode), or an “unlighted discharge cell mode” (that is, an inoperative mode) based on the input video signal, and an emission sustain step Ic, in which only the discharge cells in the “lighted discharge cell mode” are caused to emit light for a period (number of times) corresponding to the weighting of each sub-field. A universal reset step Rc that initializes all the discharge cells of the PDP to “lighted discharge cell mode” is executed only in the leading sub-field SF1. An erasing step E is executed only in the last sub-field SF12.
FIG. 2 shows a pixel data conversion table and a discharge cell emission driving pattern such as those disclosed in Japanese Patent Kokai No.2001-154630A for example.
Pixel data, for example 8-bit pixel data, can be obtained by sampling the video signal. The pixel data is subjected to multi-gradation processing. With this processing, multi-gradation pixel data PDs are generated that reduce the bit number to 4 bits while sustaining the actual number of gradations. The multi-gradation pixel data PDs are converted to pixel driving data GD made up of 1st to 12th bits in accordance with a conversion table such as that shown in FIG. 2. The 1st to 12th bits correspond to the sub-fields SF1 to SF12, respectively.
FIG. 3 shows the timing for applying the various driving pulses, which are applied to the row electrodes and column electrodes of the PDP in accordance with the emission driving format shown in FIG. 2. A known example of this is disclosed in Japanese Patent Application Kokai No. 2001-154630. It should be noted that FIG. 3 shows the case of driving by a selective erasing method (one reset/one selective erasure addressing method).
In the universal reset step Rc of sub-field SF1, a negative reset pulse RPX is applied to the row electrodes X1 to Xn. At the same time as the reset pulse RPX is applied, a positive reset pulse RPY is applied to the row electrodes Y1 and Yn. All the discharge cells of the PDP are reset and discharged in response to the reset pulses RPX and RPY, and a predetermined wall charge is formed uniformly in the discharge cells. This initializes all the discharge cells to the “lighted discharge cell mode.”
In the addressing step Wc of each sub-field, pixel data pulses DP are generated that have voltages corresponding to the logic level of the pixel driving data bits DB1 to DB12. The pixel driving data bits DB1 to DB12 correspond to the first through twelfth bits of the pixel driving data GD. For example, in the addressing step Wc of sub-field SF1, the pixel driving data bit DB1 is first converted to a pixel data pulse that has a voltage corresponding to that logic level. The pixel data pulse groups DP11 to DP1n are each successively applied to the column electrodes D1 to Dm, with m pixel data pulses corresponding to the first row applied as pixel data pulse group DP11, m pixel data pulses corresponding to the second row applied as pixel data pulse group DP12, and m pixel data pulses corresponding to the n-th row applied as pixel data pulse group DP1n.
Furthermore, in the addressing step Wc, negative scan pulses SP are successively applied to the row electrodes Y1 to Yn at the same timing as the timing of each application of the pixel data pulse groups DP. At this time, discharges (selective erasing discharges) are caused only at the discharge cells at the intersections between the row electrodes to which a scan pulse SP has been applied and the column electrodes to which a high-voltage pixel data pulse has been applied, and the wall charge remaining within the discharge cells is selectively erased.
With this selective erasing discharge, the discharge cells that were initialized to the “lighted discharge cell mode” at the universal reset step Rc transition to the “unlighted discharge cell mode.” On the other hand, the discharge cells in which no selective erasing discharge is induced sustain the state to which they have been initialized at the universal reset step Rc, that is, the “lighted discharge cell mode.”
As shown in FIG. 3, in the emission sustain step Ic of each sub-field, positive sustain pulses IPX and IPY are alternately applied to the row electrodes X1 to Xn and Y1 to Yn. The number of applications of the sustain pulse IP in each emission sustain step Ic is set to a predetermined proportion for each of the sub-fields SF1 to SF12. For example, as shown in FIG. 1, the number of times of application of sustain pulses IP for each sub-field is set to the ratio SF1:SF2:SF3:SF4:SF5:SF6:SF7:SF8:SF9:SF10:SF11:SF12=1:2:4:7:11:14:20:25:33:40:48:50.
Only the discharge cells in which the wall charge remains, that is, only the discharge cells that have been set to the “lighted discharge cell mode” in the addressing step Wc, have a discharge sustained every time the sustain pulses IPX and IPY are applied. Thus, the discharge cells that are set to the “lighted discharge cell mode” sustain an emission state with that sustain discharge for the number of times that is assigned to each sub-field.
An erasing step E is executed only for the last sub-field SF12. In the erasing step E, a positive erasing pulse AP is generated, and applied to the column electrodes D1 to Dm. Furthermore, a negative erasing pulse EP is generated with the same timing as the timing for applying the positive erasing pulse AP, and is applied to the row electrodes Y1 to Yn. An erasing discharge is induced in all the discharge cells of the PDP by the simultaneous application of these erasing pulses AP and EP, and all the wall charges that remain in the discharge cells are extinguished. All the discharge cells in the PDP go into the “unlighted discharge cell mode” due to the erasing discharges.
In the above-described driving method, it is only in one of the sub-fields that a selective erasing discharge occurs in the addressing step, and only for discharge cells that are in a light-emitting state in the immediately preceding sub-field. This causes successive lighting starting with the leading sub-field, and with N (for example 12) sub-fields, N+1 (for example 13) gradations can be displayed. Gradations are displayed by the total number of light emissions of the sustain discharges for each sub-field, in accordance with the input video signal.
Human vision has logarithmic characteristics, and humans are sensitive, for example, to tone changes in images that show dark scenes. However, by driving a PDP as described above, selective erasing discharges accompanied by light emissions are induced even when displaying black images in which the luminance is zero as shown in FIG. 2. Thus, there is the problem that the so-called dark contrast, which is the contrast for displaying images that show dark scenes, deteriorates.